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// array/map of pointers which all point
// to the functions which the index corresponds to.
// use that like a sort of map
AddData idata; //Instruction Data
// Load and Store Instructions
// the load and store instructions are currently
// used to express how data structures will work eventually.
void fLDA(Addressing addr, address val){ idata = fAddress(addr, val);
acc = idata.val;
}
void fLDX(Addressing addr, address val){ idata = fAddress(addr, val);
X = idata.value;
}
void fLDY(Addressing addr, address val){ idata = fAddress(addr, val);
Y = idata.value;
}
void fSTA(Addressing addr, address val){ idata = fAddress(addr, val);
Memory[idata.value] = acc;
}
void fSTX(Addressing addr, address val){ idata = fAddress(addr, val);
Memory[idata.value] = X;
}
void fSTY(Addressing addr, address val){ idata = fAddress(addr, val);
Memory[idata.value] = Y;
}
// Arithmetic Instructions
instruction_data fADC(Addressing addr, address val){
instruction_data d; d.length = getLength(addr);
int buffer = acc + fAddress(addr, val);
setFlagV(buffer, acc);
if (buffer > 255){
flagSet(flag_C);
}else{
flagClear(flag_C);
}
acc += fAddress(addr, val);
setFlagN(acc);
setFlagZ(acc);
}
instruction_data fSBC(Addressing addr, address val){
int buffer = acc - fAddress(addr, val);
setFlagV(buffer, acc);
if (buffer < 0){
flagSet(flag_C);
}else{
flagClear(flag_C);
}
acc -= fAddress(addr, val);
setFlagN(acc);
setFlagZ(acc);
}
//Increment and Decrement Instructions
instruction_data fINC(Addressing addr, address val){
Memory[x]++;
setFlagD(Memory[x]);
setFlagZ(Memory[x]);
}
instruction_data fINX(){
X++;
setFlagD(X);
setFlagZ(X);
}
instruction_data fINY(){
Y++;
setFlagD(Y);
setFlagZ(Y);
}
instruction_data fDEC(Addressing addr, address val){
Memory[x]--;
setFlagD(Memory[x]);
setFlagZ(Memory[x]);
}
instruction_data fDEX(){
X--;
setFlagD(X);
setFlagZ(X);
}
instruction_data fDEY(){
Y--;
setFlagD(Y);
setFlagZ(Y);
}
// Logical Instructions
instruction_data fAND(Addressing addr, address val){
acc = acc & fAddress(addr, val);
setFlagN();
setFlagZ(acc);
}
instruction_data fORA(Addressing addr, address val){
acc = acc | fAddress(addr, val);
setFlagN();
setFlagZ(acc);
}
instruction_data fEOR(Addressing addr, address val){
acc = acc ^ fAddress(addr, val);
setFlagN(acc);
setFlagZ(acc);
}
// Jump, Branch, Compare, and Test Bits
instruction_data fJMP(address val){
PC = val;
}
instruction_data fBCC(signed char val){
if (getFlag(flag_C) == 0) PC += val;
}
instruction_data fBCS(signed char val){
if (getFlag(flag_C) == 1) PC += val;
}
instruction_data fBEQ(signed char val){
if (getFlag(flag_Z) == 1) PC += val;
}
instruction_data fBNE(signed char val){
if (getFlag(flag_Z) == 0) PC += val;
}
instruction_data fBMI(signed char val){
if (getFlag(flag_N) == 1) PC += val;
}
instruction_data fBPL(signed char val){
if (getFlag(flag_N) == 0) PC += val;
}
instruction_data fBVS(signed char val){
if (getFlag(flag_V) == 1) PC += val;
}
instruction_data fBVC(signed char val){
if (getFlag(flag_V) == 0) PC += val;
}
instruction_data fCMP(address val){
if (acc < Memory[val]){
flagSet(flag_N); flagClear(flag_Z); flagClear(flag_C);
}if (acc == Memory[val]){
flagClear(flag_N); flagSet(flag_Z); flagClear(flag_C);
}if (acc > Memory[val]){
flagClear(flag_N); flagClear(flag_Z); flagSet(flag_C);
}
}
instruction_data fCPX(address val){
if (X < Memory[val]){
flagSet(flag_N); flagClear(flag_Z); flagClear(flag_C);
}if (X == Memory[val]){
flagClear(flag_N); flagSet(flag_Z); flagClear(flag_C);
}if (X > Memory[val]){
flagClear(flag_N); flagClear(flag_Z); flagSet(flag_C);
}
}
instruction_data fCPY(address val){
if (Y < Memory[val]){
flagSet(flag_N); flagClear(flag_Z); flagClear(flag_C);
}if (Y == Memory[val]){
flagClear(flag_N); flagSet(flag_Z); flagClear(flag_C);
}if (Y > Memory[val]){
flagClear(flag_N); flagClear(flag_Z); flagSet(flag_C);
}
}
instruction_data fBIT(address val){
setFlag(flag_N, (Memory[val] & flag_N));
setFlag(flag_V, (Memory[val] & flag_V));
if (((Memory[val] & flag_N) & (Memory[val] & flag_V)) == 0) {
flagSet(flag_Z);
} else {
flagSet(flag_Z);
}
}
// Shift and Rotate Instructions
instruction_data fASL(Addressing addr, address val){
setFlag(flag_C, (val & 0x80));
acc = (val << 1);
setFlagN(acc);
setFlagZ(acc);
}
instruction_data fASL(Addressing addr, address val){
setFlag(flag_C, (val & 0x01));
acc = (val >> 1);
setFlagN(acc);
setFlagZ(acc);
}
instruction_data fROL(Addressing addr, address val){
setFlag(flag_C, (val & 0x80));
acc = (val << 1);
acc |= (getFlag(flag_C) * 0x01);
setFlagN(acc);
setFlagZ(acc);
}
instruction_data fROR(Addressing addr, address val){
setFlag(flag_C, (val & 0x01));
acc = (val >> 1);
acc |= (getFlag(flag_C) * 0x80);
setFlagN(acc);
setFlagZ(acc);
}
// Transfer Instructions
instruction_data fTAX(){
X = acc;
setFlagN(X);
setFlagZ(X);
}
instruction_data fTAY(){
Y = acc;
setFlagN(Y);
setFlagZ(Y);
}
instruction_data fTXA(){
acc = X;
setFlagN(acc);
setFlagZ(acc);
}
instruction_data fTYA(){
acc = Y;
setFlagN(acc);
setFlagZ(acc);
}
// Stack Instructions
instruction_data fTSX(){
X = S;
}
instruction_data fTXS(){
S = X;
}
instruction_data fPHA(){
}
instruction_data fPHP(){
}
instruction_data fPLA(){
}
instruction_data fPLP(){
}
// Subroutine Instructions
// Set/Reset Insutrctions
instruction_data fCLC(){
flagClear(flag_C);
return {1, 2};
}
instruction_data fCLD(){
flagClear(flag_D);
return {1, 2};
}
instruction_data fCLI(){
flagClear(flag_I);
return {1, 2};
}
instruction_data fCLV(){
flagClear(flag_V);
return {1, 2};
}
instruction_data fSEC(){
flagSet(flag_C);
return {1, 2};
}
instruction_data fSED(){
flagSet(flag_D);
return {1, 2};
}
instruction_data fSEI(){
flagSet(flag_I);
return {1, 2};
}
// NOP/BRK Instructions
instruction_data fNOP(){
return {1, 2};
}
instruction_data fBRK(){
flagSet(flag_B);
return {1, 7};
}
/*
void runInstruction(int code, int val){
switch(code){
}
}
*/
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